Photoelectric conversion apparatus

ABSTRACT

Providing a configuration that, when an AD converter is provided for each of pixel columns, enables each of the elements to be arranged without increasing the element arrangement pitch. A photoelectric conversion apparatus according to the present invention includes a plurality of AD converters. The AD converter includes: an arithmetic operation amplifying circuit unit, a comparator circuit unit for comparing, with a reference signal, an output from the arithmetic operation amplifying circuit unit; a DA converted circuit unit for DA converting a signal based on a signal from the comparator circuit unit; and a sampling and holding unit arranged at an input section of the arithmetic operation amplifying circuit unit. The DA converted circuit unit is arranged between the comparator circuit unit and the arithmetic operation amplifying circuit unit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a photoelectric conversion apparatus,and more specifically relates to an arrangement of an AD converter thatconverts analog signals obtained by means of photoelectric conversion todigital signals.

2. Description of the Related Art

Currently, MOS-type photoelectric conversion apparatuses are used forphotoelectric conversion apparatuses employed in digital cameras anddigital video recorders and the like. An MOS-type photoelectricconversion apparatus has many advantages compared to a CCD or the like,because circuits, such as a circuit for controlling the reading ofsignals from pixels and a circuit for processing output signals, can beformed in the same processes. In recent years, there arises a need forfurther increasing the speed of signal output in MOS-type photoelectricconversion apparatuses, and as one of the techniques for meeting thatneed, a construction having a plurality of AD converters each providedfor each of a plurality of pixels, has been considered. For example, anAD converter can be provided for each of the pixel columns in theconstruction where pixels are arranged in a matrix such that analog datacan be converted to digital data by column, thereby increasing thespeed.

As one of such constructions, Japanese Patent Application Laid-Open No.2005-136540 discloses a photoelectric conversion apparatus having arecursive AD converter provided for each column. This apparatus has aphotoelectric conversion region with a plurality of pixels arrangedtherein, and a plurality of AD converters, arranged on the samesemiconductor substrate.

The recursive AD converter disclosed in Japanese Patent ApplicationLaid-Open No. 2005-136540 repeats comparison with a reference signal andamplification via an arithmetic amplifying circuit and a DA conversioncircuit to calculate the result, starting from a higher order bit. Suchrecursive AD converter requires a path for feeding a signal obtained bydecoding an output from a comparator back to a DA converter.

Conventionally, no sufficient consideration has been made for therelationship between this feedback path and the arrangement of elementsconstituting an AD converter. The present inventors' study has revealedthat where the elements are arranged following the flow of a signal inthe AD converter, the arrangement pitch of the elements constituting theAD converter may determine the arrangement pitch per pixel column.

In view of such technical problems, an object of the present inventionis to provide a configuration that, when an AD converter is provided foreach of pixel columns or each plurality of pixel columns, enables theelements to be arranged without increasing the element arrangement pitchfor the pixel columns.

SUMMARY OF THE INVENTION

In view of the aforementioned problems, the present invention provides aphotoelectric conversion apparatus having a plurality of AD converterseach provided for each of a plurality of pixels, the plurality of ADconverters and the plurality of pixels being arranged in the samesemiconductor substrate, wherein a signal line is provided fortransmitting a signal from the plurality of pixels to the plurality ofAD converters, the AD converter comprises: an arithmetic operationamplifying circuit unit for inputting as an input signal the signal fromthe signal line; a comparator circuit unit for comparing, with areference signal, an output from the arithmetic operation amplifyingcircuit unit; a DA converted circuit unit for DA converting a signalbased on a signal from the comparator circuit unit; and a sampling andholding unit arranged at an input section of the arithmetic operationamplifying circuit unit to hold the input signal of the arithmeticoperation amplifying circuit unit, and the comparator circuit unit isarranged in a first region of the semiconductor substrate, thearithmetic operation amplifying circuit unit is arranged in a secondregion of the semiconductor substrate, and the DA converted circuit unitis arranged in a third region between the first and second regions ofthe semiconductor substrate.

Other features and advantages of the present invention will be apparentfrom the following description taken in conjunction with theaccompanying drawings, in which like reference characters designate thesame or similar parts throughout the figures thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating an example of a photoelectricconversion apparatus according to the present invention.

FIG. 2 is a diagram illustrating an example of an AD converter accordingto the present invention.

FIG. 3 is a schematic diagram illustrating a wiring arrangement in an ADconverter according to a first embodiment.

FIG. 4 is a schematic diagram illustrating a wiring arrangement in an ADconverter according to a second embodiment.

FIG. 5 is a schematic diagram for describing an example of drive pulsesfor a photoelectric conversion apparatus according to a secondembodiment.

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate embodiments of the invention and,together with the description, serve to explain the principles of theinvention.

DESCRIPTION OF THE EMBODIMENTS

Preferred embodiments of the present invention will now be described indetail in accordance with the accompanying drawings.

First Embodiment

FIG. 1 is a schematic diagram for describing a photoelectric conversionapparatus according to the present invention. FIG. 1 shows asemiconductor substrate 1. Pixels 2 each include a photoelectricconversion element that performs photoelectric conversion of incidentlight, and a switch, such as an MOS transistor, for reading signalsaccumulated in the photoelectric conversion element. Signals from thepixels are transferred via the respective signal lines 3 to ADconverters arranged for the respective columns. In a region 4, aplurality of AD converters each provided for each plurality of pixels isarranged. For example, one AD converter is arranged for one column in amatrix of pixels. The plurality of pixels 2 and the plurality of ADconverters are arranged in the same semiconductor substrate 1. Each oneof the AD converters may be provided correspondingly to one column ofthe matrix of the pixels, or two or more of the AD converters may beprovided correspondingly to one column of the matrix of the pixels.

FIG. 2 illustrates an example of an AD converter provided for eachcolumn or each plurality of columns.

The AD converter includes: a comparator circuit unit 101; an arithmeticoperation amplifying circuit unit 102; a sampling and holding unit 103;a capacitor C1 for sampling and holding signals from the pixels; afeedback capacitor C2 for the arithmetic operation amplifying circuitunit; and a circuit element group 104 including the capacitors C1 andC2, a switch provided at an input terminal of the arithmetic operationamplifying circuit unit, and a switch provided in a feedback path.

The AD converter also includes: a DA converted circuit unit 105; aninput section 106 of the AD converter to which signals from a pluralityof pixels are input; and a wiring 107. The wiring 107 functions as asignal path that transfers an output from the arithmetic operationamplifying circuit unit 102 to the comparator circuit unit 101.Hereinafter, the term “wiring” refers to one that functions as a signalpath that conveys signals between different devices or nodes.

The AD converter also includes: a decoder unit 116 that decodes theresult of comparison between an output from the arithmetic operationamplifying circuit unit, the output having been processed in thecomparator circuit unit, and a reference signal; wirings 111 and 112that transfer outputs from the comparator circuit unit to the decoderunit; wirings 108, 109 and 110 that transfer signals after the processin the decoder unit to the DA converted circuit unit; and a group ofswitches 113 to 115 included in the DA converted circuit unit. Theswitches 113 to 115 are driven by signals from the wirings 108 to 110.The switch 114 is a switch for sampling and holding signals from thepixels, which are sent to the capacitor Cl via a signal line. The ADconverter can be operated in such a manner as one disclosed in JapanesePatent Application Laid-Open No. 2005-136540.

Where a photoelectric conversion apparatus has such an AD converter as acomponent, as the pixels in the photoelectric conversion apparatusbecome finer (for example, the pixel arrangement pitch becomes 2.0 μm orless), a larger limitation is imposed on the arrangement of the ADconverter on the semiconductor substrate. Thus, it becomes necessary toarrange all of the elements constituting the AD converter in a smallregion. In addition, it is necessary to provide such arrangement withoutincreasing the number of wiring layers. The necessary number of wiringsincluded in the AD converter is predetermined, and the necessary numberof wirings does not change even though the pixel arrangement pitchbecomes finer. For a general device, where the pixel arrangement pitchis made to be finer and all of the wirings in the AD converter can notbe included in one wiring layer, it is conceivable to provide multiplewiring layers. However, for a photoelectric conversion apparatus, it isnecessary to make the distance from a light receiving of a photoelectricconversion element to the outermost surface of the photoelectricconversion apparatus as short as possible for easy collection ofincident light. Accordingly, it is not favorable to increase the numberof wiring layers without careful consideration because such increase maycause deterioration of the properties of the photoelectric conversionapparatus. Accordingly, given that the number of wiring layers cannot beincreased to avoid deterioration of the properties as a photoelectricconversion apparatus, it is inevitable to make the arrangement pitch forthe AD converter wider than the pixel arrangement pitch. However, thepixel arrangement pitch does not depend on the AD converter pitch, buton the necessary number of pixels and the optical format used for thecamera. Also, the number of pixel columns handled by one AD converter isdetermined by the signal reading speed, and thus, the number of pixelcolumns handled cannot be determined according to the arrangement pitchrequired by the AD converter.

As described above, more consideration has been needed for an ADconverter arrangement that provides a finer pixel arrangement pitch,while maintaining or enhancing the properties of the photoelectricconversion apparatus. Meanwhile, as a result of diligent study, thepresent inventors have made the present invention that enables easyarrangement of an AD converter in a small pixel arrangement pitchwithout deteriorating the properties as a photoelectric conversionapparatus.

FIG. 3 shows an embodiment of an arrangement of an AD converteraccording to an embodiment of the present invention in a semiconductorsubstrate. The components having the same functions as those shown inFIG. 2 are provided with the same reference numerals and the detaileddescription thereof will be omitted. The regions provided with letter“A” in addition to the reference numerals are regions of thesemiconductor substrate 1 where the respective circuit units arearranged.

A comparator circuit unit 101 is arranged in a first region 101A of asemiconductor substrate 1, and an arithmetic operation amplifyingcircuit unit 102 is provided in a second region 102A of thesemiconductor substrate 1. A DA converted circuit unit 105 is arrangedin a third region 103A between the first region 101A and the secondregion 102A. Such arrangement prevents the wirings from being arrangeddensely in a particular region, and enhances the degree of freedom forthe wiring arrangement in the AD converter.

Here, where the respective circuit units are connection in such a manneras shown in FIG. 2, the wirings connecting the respective circuit unitscan be shortened by arranging the circuit units and element groups inthe order of signal conveyance. In other words, where the DA convertedcircuit unit 105, the arithmetic operation amplifying circuit unit 102and the comparator circuit unit 101 are arranged in the semiconductorsubstrate in this order, the wirings connecting the circuit units can beshortened. However, such arrangement increases the number of wiringsrunning over the arithmetic operation amplifying circuit unit, whichresults in a wider AD converter arrangement pitch. Using multiple wiringlayers, the wirings can be allocated to different wiring layers,enabling the arrangement without increasing the pitch. However, asdescribed above, the number of wiring layers should be small in aphotoelectric conversion apparatus, and accordingly, it may be difficultto provide multiple wiring layers for wirings arranged in the columndirection.

Here, the reason why the number of wirings running in the columndirection over the arithmetic operation amplifying circuit unit isparticularly large will be described. An arithmetic operation amplifyingcircuit is a circuit configured by combining, for example, adifferential amplifying circuit and an impedance conversion circuit, andrequires a minimum of five transistors. Furthermore, where a high openloop gain is necessary, or where it is necessary to drive a large load,the number of transistors should be further increased and accordingly, alarge number of transistors are required. In order to include thesetransistors in the arrangement pitch determined by the pixel arrangementpitch, it is necessary to closely arrange the transistors in the columndirection. With such arrangement, there is no choice but to arrange thewirings for connecting the transistors in such a manner that the wiringsextend in one direction such as the column direction. Accordingly, alarge number of wirings connecting the transistors included in thearithmetic operation amplifying circuit need to be arranged over thearithmetic operation amplifying circuit unit. In such a situation,further arrangement of the wirings 108, 109 and 110 constituting afeedback loop from a decoder to the DA converted circuit unit over thearithmetic operation amplifying circuit increases the arrangement pitchfor the AD converter. More specifically, where, viewed from thecomparator circuit unit, the DA converted circuit unit is arranged onthe opposite side across the arithmetic operation amplifying circuitunit, the number of wiring layers arranged over the arithmetic operationamplifying circuit increases by at least three (108 to 110). In otherwords, the arrangement pitch for the wring layer including the wiringsextending in at least the column direction will be increased by thetriple of the sum of the minimum wiring width and the interval betweenthe minimum wirings (i.e., line and space). When wirings are arranged soas to cover the entire arithmetic operation amplifying circuit unit,feedback wirings need to be arranged so as to avoid the arithmeticoperation amplifying circuit unit, which increases the arrangement pitchfor the AD converter by that amount.

Meanwhile, arrangement of the circuits as shown in FIG. 3 enablesreduction of the wirings extending in the column direction, which arearranged in the second region 102A where the arithmetic operationamplifying circuit unit is arranged, and thus, the arrangement pitch forthe AD converter can be decreased.

Next, an example of allocation of wirings to the respective wiringlayers will be described. For example, there are three wiring layers intotal, wiring extending in the column direction are allocated mainly toa first layer, which is the lowermost layer, control wirings extendingin the row direction are mainly allocated to a second layer, whichfollows the first layer, and power supply lines extending in the rowdirection are mainly allocated to a third layer, which is the uppermostlayer. Here, the wirings included in the first layer are used for dataconveyance between the circuit units included in the AD converter, localconnections in the circuits, configuration of a negative feedback loopin the AD converter, and transmission of signals from the comparator tothe DA converter. The wirings included in the second layer are used forsupply of a control signal to determine the timing for an operationperformed simultaneously in the respective columns. An example of thewirings is a wiring for controlling the time for a sampling and holdingoperation of a column signal in each column. The wirings included in thethird layer are used for supplying a reference voltage or a drivevoltage in common to the DA converted circuit unit, the comparatorcircuit unit, the arithmetic operation amplifying circuit unit and thelike in each column. Also, FIG. 3 shows main ones from among the wiringsincluded in the lowermost first layer. The number of these wiringschanges according to the number of transistors.

Also, even when there are two or more wiring layers extending in thecolumn direction, a similar effect can be obtained. This example enablesreduction of the number of wirings extending in the column directionover the arithmetic operation amplifying circuit unit.

Furthermore, in this example, considering the connection between the DAconverted circuit unit and the sampling and holding unit, thearrangement viewed from an input section (VIN) of the AD converter ismade as follows so that the DA converted circuit unit and the samplingand holding unit are close to each other. The region 102A where thearithmetic operation amplifying circuit unit is provided, a region 104Awhere a circuit element group is provided, the region 103A where thesampling and holding unit is provided, a region 105A where the DAconverted circuit unit is provided, and a region 101A where thecomparator circuit unit is provided are arranged in this order. Asdescribed with reference to FIG. 2, a signal from the DA convertedcircuit unit is input to the sampling and holding unit. Accordingly,such arrangement can reduce the number of wirings over the arithmeticoperation amplifying circuit unit while shortening the signal path fromthe DA converter to the sampling and holding unit.

The embodiment described above enables an AD converter to be arranged ina favorable manner in a pitch determined by a pixel arrangement pitch orthe like, without deteriorating the properties of the photoelectricconversion apparatus even when a finer pixel arrangement pitch isemployed.

Second Embodiment

FIG. 4 is a schematic diagram of an arrangement in an AD converteraccording to a second embodiment. The components having the samefunctions as those of the first embodiment are provided with the samereference numerals and the detailed description thereof will be omitted.Also, for the overall configuration of the photoelectric conversionapparatus, one shown in the schematic diagram in FIG. 1 can be employed.

The second embodiment is different from the first embodiment in that aconnection control switch is provided between an input section of an ADconverter to which signals from pixels are input and a signal line. InFIG. 4, the connection control switch is arranged in a region 201A. Inother words, a switch is added at a stage preceding the sampling andholding switch 114 in FIG. 2. The provision of this connection controlswitch controllably enables electric connection between the AD converterand the signal line.

A drive sequence of the present embodiment including the connectioncontrol switch will be described with reference to FIG. 5. FIG. 5represents an ongoing pipeline operation that performs an operation tooutput an output from the pixel in a certain row (for example, the n-throw) to the signal line and an operation to perform AD conversion of asignal from the pixel in the n−1th row, the signal being held by thesampling and holding unit 103, in parallel.

Pixel rows to be read are controlled in synchronization with pulses of ahorizontal synchronizing signal 301. A column signal line analog signal302 indicates voltage changes in the signal line, and is based on thesignals from the pixels. Pulses 303 control the sampling and holdingswitch 114. The switch is turned on at a “High” level, and holds asignal from the signal line (voltage of the signal line). Pulses forenabling AD conversion operations are collectively illustrated as apulse group 304. During the periods in which these pulses are at a“High” level, an actual AD conversion is performed for the respectivepixel rows. Pulses 305 are supplied to the connection control switchnewly provided in the present embodiment. The switch is turned on whenthe pulses are at a “High” level. The driving of the present embodimentwill be described based on FIG. 5.

First, a read operation for the n-th row starts at time 306. The voltageof the signal line changes based on a signal from the pixel. At time 307when the voltage of the signal line becomes stable, the sampling andholding switch is turned on and the sampling and holding unit samplesthe voltage of the signal line as an input signal for the AD converter.

Next, the pulse supplied to the switch 114 is made to be low at time308. Subsequently, the pulse supplied to the connection control switchis made to be low to turn the switch off at time 309. AD conversion of apixel signal in the n-th row is started at time 310, and a signal fromthe pixel in the following n+1th row is read to the signal line. Thevoltage of the signal line changes based on the pixel signal. The aboveoperation is repeated for each row.

Here, the effect of the connection control switch being added will bedescribed. The addition of this switch enables the control of electricconnection between the signal line and the AD converter, whereby theeffect of voltage changes in the signal line can be prevented from beingimposed on the AD converter. When a signal line and an AD converter areelectrically connected, a voltage change in the signal line affects anAD conversion operation via a parasitic capacitance. However, additionof a connection control switch enables the electric connection betweenthe AD converter and the signal line to be disconnected during an ADconversion operation, whereby the effect of voltage changes in thesignal line can be prevented from being imposed on the AD conversionoperation. This is highly effective especially where it is difficult toarrange the sampling and holding unit close to the signal line.

This is particularly important where the circuit units are arranged asillustrated in FIG. 4. As described for the first embodiment, where thenumber of wirings over the arithmetic operation amplifying circuit unitis reduced while the signal path from the DA converter to the samplingand holding unit being shortened, it is difficult to arrange thesampling and holding unit close to the signal line. In such a case,particularly, the AD converter is susceptible to voltage changes in thesignal line, and accordingly, it is highly effective to provide aconnection control switch.

Also, the effect of voltage changes in the signal line may be a largeproblem especially in high-bit AD conversion, and accordingly, a highadvantageous effect can be obtained especially when an AD converter withresolution of 14 bits or more, for example, is used.

Although the present invention has been described above by referring toembodiments, the present invention is not limited to these embodiments,and changes and combinations can arbitrarily be adopted as far as theydo not fall out of the spirit and scope of the present invention. Forexample, although the description has been made on a recursive ADconverter using a 1.5-bit single end MDAC (Multiplying Digital-To-AnalogConverter) for the AD converter, an AD converter using a 1-bit singleend MDAC or a 1.5-bit total differential type MDAC may also be employed.In addition, a similar advantageous effect can be exerted where anactive amplification is performed in a DA converter in a successiveapproximation-type AD converter or where double integration-type ADconverter is used. The present invention can be employed for an ADconverter requiring an arithmetic operation amplifying circuit thatsubstantially occupies the wirings in the wiring layer including wiringsextending in the column direction. A wiring that conveys feedbacksignals from the comparator circuit unit is arranged so as not to runover the arithmetic operation amplifying circuit, enables an arrangementpitch required for a column AD converter to be decreased, and suchadvantageous effect can be exerted irrespective of the AD convertertype.

Also, although the description has been made on the mode in whichsignals are read from the pixels directly to the signal line, anamplifier (column amplifier) may be provided for each pixel column or aCDS-processing clamp circuit that suppresses reset noise in the pixelsmay be provided. Also, for an operation timing for reading, thedescription has been made based on a pipeline operation that performs anoperation for reading a signal from a pixel and an AD conversionoperation in parallel, but the present invention is not limited to thiscase, and a configuration with which these operations are sequentiallyperformed may be employed. Furthermore, the voltage value of the signalline during an AD conversion may become unstable due to initializationof the pixels, which may affect the AD conversion operation. The switchadded in the second embodiment can prevent such effect from beingimposed on the AD conversion operation.

Both of the aforementioned embodiments are mere examples of embodimentsfor practicing the present invention, and the technical scope of thepresent inventions should not be interpreted to be limited by theseembodiments. In other words, the present invention can be practiced invarious manners as far as the practice does not fall out of thetechnical idea or the main features of the present invention.

This application claims the benefit of Japanese Patent Application No.2007-178394, filed Jul. 6, 2007, which is hereby incorporated byreference herein in its entirety.

1. A photoelectric conversion apparatus having a plurality of ADconverters each provided for each of a plurality of pixels, theplurality of AD converters and the plurality of pixels being arranged inthe same semiconductor substrate, wherein a signal line is provided fortransmitting a signal from the plurality of pixels to the AD converter,the AD converter comprises: an arithmetic operation amplifying circuitunit for inputting as an input signal the signal from the signal line; acomparator circuit unit for comparing, with a reference signal, anoutput from the arithmetic operation amplifying circuit unit; a DAconverted circuit unit for DA converting a signal based on a signal fromthe comparator circuit unit; and a sampling and holding unit arranged atan input section of the arithmetic operation amplifying circuit unit tohold the input signal of the arithmetic operation amplifying circuitunit, and the comparator circuit unit is arranged in a first region ofthe semiconductor substrate, the arithmetic operation amplifying circuitunit is arranged in a second region of the semiconductor substrate, andthe DA converted circuit unit is arranged in a third region between thefirst and second regions of the semiconductor substrate.
 2. Thephotoelectric conversion apparatus according to claim 1, wherein thepixels are arranged in a matrix configuration, such that each one of theAD converters is provided correspondingly to one column of the matrix ofthe pixels.
 3. The photoelectric conversion apparatus according to claim1, wherein the pixels are arranged in a matrix configuration, such thattwo or more of the AD converters are provided correspondingly to onecolumn of the matrix of the pixels.
 4. The photoelectric conversionapparatus according to claim 1, wherein the sampling and holding unit isarranged in a fourth region between the second third regions of thesemiconductor substrate.
 5. The photoelectric conversion apparatusaccording to claim 1, further comprising: a switch arranged between thesignal line and the AD converter for controlling electrical connectionbetween the signal line and the AD converter.
 6. The photoelectricconversion apparatus according to claim 1, wherein the AD converter is arecursive AD converter.